The present invention relates to a counting circuit and, more particularly, to a high-speed counting circuit that enables random data input and an address counter using the same.
FIG. 1 is a block diagram showing the construction of a general high-speed counter.
A general high-speed counter 100 includes first to fourth flip-flops (FFs) 110 to 140 and first and second OR gates OR1, OR2. The high-speed counter 100 employs a ring counter structure and performs a 2-bit counting operation.
Each of the first to fourth FFs 110 to 140 has an input terminal D and an output terminal Q. A signal input to the input terminal D is output to the output terminal Q according to a clock CLK. Each of the first to fourth FFs 110 to 140 includes a set terminal S and a reset terminal R.
The input terminal D of the first FF 110 and the output terminal Q of the fourth FF 140 are connected. A preset control signal PRE is input to the set terminal S of the first FF 110. The output terminal Q of the first FF 110 is coupled to the input terminal D of the second FF 120. The output terminal Q of the second FF 120 is coupled to the input terminal D of the third FF 130.
The output terminal Q of the third FF 130 is coupled to the input terminal D of the fourth FF 140. The clock signal CLK is input to a clock terminal CK of each of the first to fourth FFs 110 to 140. The preset control signal PRE is input to the reset terminals R of the second to fourth FFs 120 to 140. The first to fourth FFs 110 to 140 are D FFs (flop-flops).
The first and second OR gates OR1, OR2 are configured to calculate the binary number of a 2-bit counter. An output signal of the third FF 130 and an output signal of the fourth FF 140 are input to the first OR gate OR1. The output of the first OR gate OR1 is a second bit B1, that is, a most significant bit (MSB).
An output signal of the second FF 120 and an output signal of the third FF 130 are input to the second OR gate OR2. The output of the second OR gate OR2 is a first bit B0, that is, a least significant bit (LSB).
The high-speed counter 100 performs a 2-bit count. This structure is called a unit counter block (UCB). In order to configure a 2N-bit counter, N high-speed counters 100 having the above UCB are required.
An operating principle of the high-speed counter 100 is described below. The first to fourth FFs 110 to 140 operate synchronously with the clock signal CLK. Thus, the first to fourth FFs 110 to 140 operate as a shift register.
The preset control signal PRE is applied to the set terminal S of the first FF 110, but to the reset terminals R of the second to fourth FFs 120 to 140. Accordingly, a reset state of the first to fourth FFs 110 to 140 becomes ‘1000’.
The high-speed counter 100 repeats states ‘1000’, ‘0100’, ‘0010’, and ‘0001’ synchronously with the clock signal CLK. The first and second bits B1, B0, that is, the outputs of the first and second OR gates OR1, OR2 are generated.
The high-speed counter 100 cannot input a reset state. That is, a reset state is always ‘1000’, which makes the counting start value of the counter always fixed to ‘0’. However, the counter does not always start from ‘0’, but sometimes has to perform a counting operation using randomly input values.
Several high-speed counters 100 may be coupled to construct a 4-bit or 8-bit counting circuit, and the output signal Q3 of the fourth FF 140 is used as a clock signal of a high-speed counter coupled to a next terminal. In this case, the output signal Q3 is not synchronized with the clock because of skew, etc potentially resulting in malfunction.